View 33389_803748.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

document number: mc33389 rev. 5.0, 3/2007 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2007. all rights reserved. system basis chip with low speed fault tolerant can the 33389 is a monolithic integrated circuit combining many functions frequently used by automo tive engine control units (ecus). it incorporates a low speed fault tolerant can transceiver. features ? dual low drop voltage regulators, with respectively 100 ma and 200 ma current capabilities, current limitation, and over temperature detection with pre-warning ? 5.0 v output voltage for v1 regulator ? three operational modes (normal, stand-by, and sleep modes) separated from the can interface operating modes ? low speed 125 kbaud fault toler ant can interface, compatible with 33388 stand alone physical interface ? v1 regulator monitoring and reset function ? three external high voltage wake-up inputs, associated with v3 v bat switch ? 100 ma output current capability for v3 v bat switch allowing drive of external switches or relays ? low stand-by and sleep current consumption ?v bat monitoring and v bat failure detection capabilities ? dc operating voltage up to 27 v ? 40 v maximum transient voltage ? programmable software window watchdog and reset ? wake-up capabilities (can interface, local programmable cycle wake ? interface with the mcu through the spi ? pb-free packaging designated by suffix codes vw and eg figure 1. 33389 simplified application diagram system basis chip dh suffix vw suffix (pb-free) plastic package 98ash70273a 20-pin hsop 33389 dw suffix eg suffix (pb-free) plastic package 98asb42345b 28-pin soicw spi mosi sck miso cs 5.0 v 5.0 v v pwr switched v bat mcu w ake-up inputs can bus twisted pair 33389 v2 v1 int rst mosi sck miso cs tx rx gnd vbat v3 l0 l1 l2 can h can l rth rtl ordering information device temperature range (t a ) package mc33389cdh/r2 -40 to 125c hsop-20 mc33389cvw/r2 mc33389cdw/r2 so-28 mc33389ddw/r2
analog integrated circuit device data 2 freescale semiconductor 33389 device variations device variations table 1. device variations freescale part no. v1 undervoltage mc33389cdh mc33389cvw mc33389cdw in v1 undervoltage condition, device remains in permanent reset state until v1 returns to normal conditions. v1 is protected by overcu rrent and overtemperature functions. mc33389ddw the sole difference between the c version an d the d version is v1 reset threshold. reference v1 reset threshold on v1 on page 9 .
analog integrated circuit device data freescale semiconductor 3 33389 internal block diagram internal block diagram figure 2. 33389 simplifi ed internal block diagram fault-tolerant can transceiver programmable wake-up inputs spi interface interrupt control reset control watchdog & oscillator dual voltage regulator voltage control battery voltage failure detect voltage monitor v bat switch supply mode control canh canl rth rtl vbat v3 v2 v1 int rst cs mosi miso sclk tx rx l1 l2 l0 gnd v 2 5v 5v
analog integrated circuit device data 4 freescale semiconductor 33389 pin connections pin connections figure 3. 33389 pin connections table 1. 33389 pin definitions: hsosp 20-lead a functional description of each pin can be found in the functional pin description section beginning on page 17 . pin number pin name formal name definition 1 tx transmitter data transmitter input of the ls can interface 2 v1 voltage regulator one this 5.0 v pin is a 3% low drop voltage regul ator dedicated to the microcontroller supply. 3 rx receiver data receiver output of the ls can interface 4 rst reset this is an input/output pin. 5 int interrupt output this output is asserted low when an enabled interrupt condition occurs. 6 miso master in/slave out this pin is the tri-state out put from the shift register. 7 mosi master out/slave in this pin is for the input of serial instruction data. 8 sclk system clock this pin clocks the inte rnal shift registers. 9 cs chip select this pin communicates with the syst em mcu and enables spi communication. 10 - 12 l0 - l2 level 0 - 2 inputs (l0: l2) input interfaces to external circuitry. level s at these pins can be read by spi and input can be used as programmable wake -up input in sleep or stop mode. 13 rth rth pin for the connection of the bus termination to canh 14 canl can low can low input/output 15 gnd ground this pin is the ground of the integrated circuit. 16 canh can high can high input/output 17 v2 voltage regulator two this 5.0 v pin is a low drop voltage regul ator dedicated to the peripherals supply. 18 rtl rtl pin for the connection of the bus termination to canl 19 vbat voltage battery this pin is voltage supply from the battery. 20 v3 voltage regulator three this pin is a 10 ? switch to v bat , used to supply external contacts or relays. v3 tx vbat rtl v2 canh gnd canl rth l0 l1 v1 int miso mosi sclk cs l2 rx rst 1 2 3 4 5 6 7 8 9 10 20 19 16 15 14 13 12 11 18 17
analog integrated circuit device data freescale semiconductor 5 33389 pin connections table 2. 33389 pin defini tions: soicw 28-lead a functional description of each pin can be found in the functional pin description section beginning on page 17 . pin number pin name formal name definition 1 tx transmitter data transmitter input of the ls can interface 2 v1 voltage regulator one this 5.0 v pin is a 3% low drop voltage regul ator dedicated to the microcontroller supply. 3 rx receiver data receiver output of the ls can interface 4 rst reset this is an input/output pin. 5 int interrupt this output is asserted low when an enabled interrupt condition occurs. 6 -9 20 - 23 gnd ground these device ground pins are internally c onnected to the package lead frame to provide a 33389-to-pcb thermal path. 10 miso master in/slave out this pin is the tri-state out put from the shift register. 11 mosi master out/slave in this pin is for the input of serial instruction data. 12 sclk system clock this pin clocks the inte rnal shift registers. 13 cs chip select this pin communicates with the syst em mcu and enables spi communication. 14, 15, 16 l0: l2 wake-up input (l0: l2) input interfaces to external circuitry. lev els at these pins can be read by spi and input can be used as programmable wake -up input in sleep or stop mode. 17 nc no connect this pin does not connect. 18 rth thermal resistance high pin for the connection of the bus termination to canh 19 canl can low can low input/output 24 canh can high can high input/output 25 v2 voltage regulator two this 5.0 v pin is a low drop voltage regul ator dedicated to the peripherals supply. 26 rtl thermal resistance low pin for the connection of the bus termination to canl 27 vbat voltage battery this pin is voltage supply from the battery. 28 v3 voltage regulator three this pin is a 10 ? switch to v bat , used to supply external contacts or relays. v3 v2 canh gnd gnd gnd gnd canl rth nc l0 l1 vbat rtl tx rst int gnd gnd gnd gnd miso mosi sclk cs l2 v1 rx 4 5 6 7 8 9 10 11 12 13 14 2 3 28 25 24 23 22 21 20 19 18 17 16 15 27 26 1
analog integrated circuit device data 6 freescale semiconductor 33389 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit electrical ratings dc voltage at vbat pin v bat -0.3 to 27 v transient voltage at vbat pin t < 500 ms (load dump) v bat 40 v dc voltage at pins canh and canl v bat -20 to 27 v transient voltage at pins canh and canl 0.0 < v2 < 5.5, v bat > 0.0, t < 500 ms v bat -40 to 40 v coupled transient voltage at pins canh and canl with 100 ? termination resistors, coupled through 1.0 nf (1) v bat -100 to 100 v dc voltage at pins v1 and v2 v bat -0.3 to 6.0 v dc current at output pins rx, miso, rst , int v bat -20 to 20 ma dc voltage at input pins tx, mosi, cs , rst v bat -0.3 to 6.0 v dc voltage at pins l0, l1, l2 0.0 < v bat < 40 v v bat -0.3 to 40 v current at pins l0, l1, l2 v bat -15 ma transient current at pin v3 v bat -30 to 20 ma dc voltage at pins rth and rtl v bat -0.3 to 40 v esd voltage on any pin (hbm 100 pf, 1.5 k) v bat -2.0 to 2.0 kv esd voltage on l0, l1, l2, canh, canl, vbat v bat -2.0 to 2.0 kv esd voltage on any pin (mm 200 pf, 0 ? ) v bat -150 to 150 v thermal ratings operating junction temperature t j -40 to 150 c ambient temperature t a -40 to 125 c storage temperature t s -55 to 165 c notes 1. pulses 1, 2, 3a, and 3b according to iso7637.
analog integrated circuit device data freescale semiconductor 7 33389 electrical characteristics maximum ratings thermal resistance rth, rtl termination resistance r rthrtl 500 to 16 k ? junction to heatsink thermal resistance for hsop-20 33% power on v1, 66% on v2 (including can) (2) r ajc 3.1 c/w junction to pin thermal resistance for so-28wd (3) r as/p 17 c/w thermal shutdown temperature t sd 165 c peak package reflow temperature during reflow (4) , (5) t pprt note 5 c notes 2. refer to thermal management in device description section. 3. refer to thermal management in device section. ground pins 6, 7, 8, 9, 20, 21, 22, and 23 of so28wb package. 4. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 5. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.freescale.com, search by part number [e.g. remove pref ixes/suffixes and enter the core id to view all orderable parts . (i.e. mc33xxxd enter 33xxx), and review parametrics. table 3. maximum ratings (continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol value unit
analog integrated circuit device data 8 freescale semiconductor 33389 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics characteristics noted under conditions v bat , - 40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit power input (vbat) nominal vbat operating range v bat 5.5 ? 18 v functional vbat operating range v bat 5.5 ? 27 v v bat threshold for bat fail flag bat fail 2.0 ? 4.0 v delay for signalling bat fail tfail ? 150 400 s overvoltage v bat threshold bat high 18 20 22 v delay for setting bat high flag t high 4.0 18 50 s supply current in sleep mode forced wake-up and cy clic sense disabled v bat = 12 v, t j = 25c to 150c i sleep1 ? 75 125 a supply current in sleep mode forced wake-up and cy clic sense disabled v bat = 12 v, t j = -40c to 25c i sleep2 ? ? 210 a supply current in sleep mode forced wake-up and cyclic sense enabled v bat = 12 v, t j = 25c to 150c i sleep3 ? 105 155 a supply current in sleep mode forced wake-up and cyclic sense enabled v bat = 12 v, t j = -40c to 25c i sleep4 ? ? 250 a supply current in sleep mode forced wake-up and cy clic sense disabled v bat = 12 v, t j = 25c to 150c i sleep5 ? ? 300 a supply current in stand-by mode i stb2 ? 0.5 1.0 ma supply current in normal mode normal mode with i(v1) = 1 i(v2) = 0 bus in recessive state i nrec ? 3.5 7.0 ma power output v1 output voltage 0 ma < i out < 100 ma 5.5 v < v bat < 27 v v1 nom 4.85 5.0 5.15 v v1 output voltage i out =< 100 ma 27 v < v bat < 40 v v1 4.8 5.0 5.2 v v1 drop voltage i out =< 100 ma (6) v1drop ? 0.35 0.5 v notes 6. measured when v1 has dropped 100mv below its nominal value
analog integrated circuit device data freescale semiconductor 9 33389 electrical characteristics static electrical characteristics power output (continued) v1 output current limitation v1 nom - 100 mv i1max 130 170 200 ma v1 overtemperature shut off threshold junction temperature tv1h 160 ? 190 c v1 pre-warning temperature threshold junction temperature tv1l 130 ? 160 c v1 temperature threshold difference tv1h-tv1l 20 ? 40 c v1 reset threshold on v1 5.5 v < v bat < 27 v (c version) (d version) vr1 4.1 v2 - 0.4 4.3 v1 - 0.28 4.8 v1 - 0.1 v v1 reset active v1 range v1r 1.0 vr1 ? v v1 reverse current from v1 to v bat and gnd v1 = 4.9 v, 0 < v bat < 4.9 v irev ? ? 1.0 ma v2 output voltage 0 ma < i out < 200 ma 5.5 v < v bat < 40 v v2nom 4.75 5.0 5.25 v v2 drop voltage i out = 200 ma (7) v2drop ? 0.2 0.5 v v2 drop voltage i out = 20 ma (7) v2drop ? 0.05 0.15 v v2 output current limitation v2 nom -100 mv i1 max 220 280 350 ma v2 threshold on v2 to report v2 off v2 nominal v r2 4.1 4.55 4.75 v v r2 delay time v r2 20 ? 70 s v2 overtemperature pre-warning threshold v2 junction temperature t v2l 130 ? 160 c v2 overtemperature switch-off threshold v2 junction temperature t v2h 155 ? 185 c v2 line regulation 9.0 v < v bat < 16.5 v2 lr1 -15 ? +15 mv v2 load regulation 4.0 ma < i load < 200 ma v2 lr2 -75 ? +75 mv v2 line ripple rejection 100 hz, 1.0 v pp on v bat (8) v2 lrr 30 55 ? db notes 7. measured when v1 has dropped 100mv below its nominal value 8. guaranteed by design; however, it is not production tested table 4. static electrical characteristics (continued) characteristics noted under conditions v bat , - 40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33389 electrical characteristics static electrical characteristics power output (continued) v2 percentage difference v2-v1 v bat > 9.0, i v1 = 20 ma, i v2 = 40 ma v2 v2-v1 -3.0 ? 3.0 % v3 high level voltage drop i v3 = -50 ma, 9.0 v < v bat < 40 v v3 drop ? 0.4 1.0 v v3 high level voltage drop i v3 = -50 ma, 6.0 v < v bat < 9.0 v v3 drop ? ? 1.5 v v3 leakage output limitation 5.5 v < v bat < 27 v i3 lim 100 150 250 ma v3 leakage current v3 = 0 (v3 off) i3 leak ? ? 15 a v3 overtemperature detection junction temperature t v3 155 ? 185 c v3 voltage with -30 ma (negative current for relay switch off) no functional error allowed for t < 100 ms v v3 0.3 ? 0.5 v can transceiver v2 for forced bus stand-by mode (fail safe) vrc2 3.0 3.9 4.7 v canh/l differential receiver, threshold voltage v canth -3.2 ? -2.5 v canh/l differential receiver, dominant to recessive threshold (bus failures 1, 2, and 5) v candrth -3.2 ? -2.5 v canh recessive output voltage tx = high, r(rth) < 4.0 k v canh ? ? 0.2 v canl recessive output voltage tx = high, r(rth) < 4.0 k v canl v2-0.2 ? ? v canh output voltage, dominant tx = 0 v, busnormal mode, i canh = - 40 ma v canh v2-1.4 ? ? v canl output voltage, dominant tx = 0 v, bus normal mode, i canl = - 40 ma v canl ? ? 1.4 v canh output current limit (v canh = 0.0 v, tx = 0) i canh 50 75 100 ma canl output current limit (v canl = 14 v, tx = 0) i canl 50 95 130 ma detection threshold for short circuit to battery voltage bus normal mode v canh -v canl 7.3 7.9 8.9 v detection threshold for short circuit to battery voltage bus stand-by mode v canh v bat /2+3 ? v bat /2+5 v canh output current, failure 3 bus stand-by mode v canh = 12 v i canhf3 ? 5.0 10 a canl output current, failure 4 bus stand-by mode, v canl = 0.0 v, v bat = 12 v i canlf4 ? 0.0 2.0 a table 4. static electrical characteristics (continued) characteristics noted under conditions v bat , - 40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33389 electrical characteristics static electrical characteristics power output (continued) canl wake-up voltage threshold bus stand-by mode v wakel 2.5 3.3 3.9 v canh wake-up voltage threshold bus stand-by mode v wakeh 1.2 2.0 2.7 v wake-up threshold difference v wakel - v wakeh 0.2 ? ? v canh single ended receiver threshold failures 4, 6, and 7 v canh 1.5 1.85 2.15 v canl single ended receiver threshold failures 3 and 8 v canl 2.8 3.05 3.4 v canl pull-up current bus normal mode i canlpu 45 75 90 a canh pull down current bus normal mode i canlpd 45 75 90 a receiver differential input impedance canh/canl r diff 100 ? 180 k ? differential receiver common mode voltage range v com -8.0 ? 8.0 v rtl to v2 switch on resistance i out < -10 ma, bus normal operating mode r rtl 10 25 70 ? rtl to battery switch series resistance bus stand-by mode r rtl 8.0 12.5 20 k ? rth to ground switch on resistance i out < 10 ma, all modes r rth ? 25 70 ? control interface high level input voltage v ih 0.7 v1 ? v1 + 0.3 v v cs threshold for spi wake-up sbc in sleep mode, v1 < 1.5 v v csth ? 2.2 ? v cs filter time for spi wake-up sbc in sleep mode, v1 < 1.0 v t csft ? ? 3.0 s low level input voltage v il -0.3 ? 0.3 v1 v high level input current on cs v i = 4.0 v i csh -100 ? -20 a low level input current on cs v i = 1.0 v i csl -100 ? -20 a tx high level input current v i = 4.0 v i txh -200 -80 -25 a tx low level input current v i = 1.0 v i txl -800 -320 -100 a si, sclk input current 0 < v in < v1 i sislk -10 ? +10 a table 4. static electrical characteristics (continued) characteristics noted under conditions v bat , - 40 c t a 125 c unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33389 electrical characteristics static electrical characteristics control interface (continued) rx, int , miso high level output voltage i 0 = -250 a v oh v1 - 0.9 ? v1 v rx, int , miso low level output voltage i 0 = -1.5 ma v ol 0.0 ? 0.9 v rx, int , miso tri-stated so output current 0 v < v so < v1 i z -2.0 ? +2.0 a rst high level input voltage v ih 0.7 v1 ? v1 + 0.3 v ? rst low level input voltage v il -0.3 ? -0.3 v1 v rst high level output current 1 0.0 < v out < 0.5 v1 i rsth1 -50 -30 -10 a rst high level output current 2 0.5 < v out < v1 i rsth2 ? -300 ? a rst low level output voltage (i 0 = 1.5 ma) 1.0 v < v bat < 27 v v rst 0.0 ? 0.9 v lx/wake-up positive switching threshold 6.0 v analog integrated circuit device data freescale semiconductor 13 33389 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit microcontroller interface ac canl/canh slew rates, rising or falling edges, tx fr om recessive to dominant state c load - 10 nf, 133 ? termination resistors t canrd 3.5 5.0 10 v/s ac canl/canh slew rates, rising or falling edges, tx from dominant to recessive state c load - 10 nf, 133 ? termination resistors t candr 2.0 3.5 10 v/s ac propagation delay tx to rx low c load - 10 nf, 133 ? termination resistors t dh ? 1.2 2.0 s ac propagation delay tx to rx high c load - 10 nf, 133 ? termination resistors t dl ? 2.0 3.0 s wake-up filter time t wuft 8.0 20 38 s rst duration after v1 high t res ? 1.0 ? ms sclk clock period t psclk 500 ? ? ns sclk clock high time t wsclkh 175 ? ? ns sclk clock low time t wsclkl 175 ? ? ns falling edge of cs to rising edge of sclk t lead 250 50 ? ns falling edge of sclk to rising edge of cs t lead 250 50 ? ns si to falling edge of sclk t sisu 125 25 ? ns falling edge of sclk to si t si(hold) 125 25 ? ns so rise time (c l = 200 pf) t rso ? 25 75 ns so fall time (c l = 200 pf) t fso ? 25 75 ns si, cs , sclk incoming signal rise time t rsi ? ? 200 ns si, cs , sclk incoming signal fall time t fsi ? ? 200 ? time from falling edge of cs to so low impedance high impedance t so(en) t so(dis) ? ? 200 200 ns time from rising edge of sclk to so data valid 0.2 v1 or v2 < so > 0.8 v1 or v2, c l = 200 pf t valid ? 50 125 ? running mode oscillator tolerance (normal request, normal and stand-by modes (9) ) rmot -12 ? +12 % software watchdog timing 1 (9) t sw1 4.4 5.0 5.6 ms software watchdog timing 2 (9) t sw2 8.8 10 11.2 ms software watchdog timing 3 (9) t sw3 17.6 20 22.4 ms software watchdog timing 4 (9) t sw4 28 32 36 ms notes 9. software watchdog timing accuracy is based on the running mode oscillator tolerance
analog integrated circuit device data 14 freescale semiconductor 33389 electrical characteristics dynamic electrical characteristics microcontroller interface (continued) software watchdog timing 5 (10) t sw5 44.8 51 58 ms software watchdog timing 6 (10) t sw6 65 74 83 ms software watchdog timing 7 (10) t sw7 88 100 112 ms software watchdog timing 8 (10) . t sw8 167 190 213 ms sleep mode oscillator tolerance (10) smot -30 ? +30 % cyclic sense/fwu timing 1 sleep mode (10) t cy1 22.4 32 46.6 ms cyclic sense/fwu timing 2 sleep mode (10) t cy2 44.8 64 83.2 ms cyclic sense/fwu timing 3 sleep mode (10) t cy3 89.6 128 166.4 ms cyclic sense/fwu timing 4 sleep mode (10) t cy4 179 256 333 ms cyclic sense/fwu timing 5 sleep mode (10) t cy5 358 512 665 ms cyclic sense/fwu timing 6 sleep mode (10) . t cy6 717 1024 1331 ms cyclic sense/fwu timing 7 sleep mode (10) t cy7 1434 2048 2662 ms cyclic sense/fwu timing 8 sleep mode (10) t cy8 5734 8192 10650 ms ground shift threshold 1 (11) can transceiver active in two wire operation gs1 -1.0 -0.7 -0.3 v ground shift threshold 2 (11) can transceiver active in two wire operation gs2 -1.5 -1.2 -0.8 v ground shift threshold 3 (11) can transceiver active in two wire operation gs3 -2.0 -1.7 -1.3 v ground shift threshold 4 (11) can transceiver active in two wire operation gs4 -2.6 -2.2 -1.7 v bus transmitter ac minimum dominant time for wake-up on canl or canh bus stand-by mode, v bat = 12 v t wake 4.0 ? 40 s ac failure 3 detection time bus normal mode t ac3d 10 ? 60 s ac failure 3 recovery time bus normal mode t ac3r 10 ? 60 s ac failure 6 detection time bus normal mode t ac6d 50 ? 400 s ac failure 6 recovery time bus normal mode t ac6r 150 ? 1000 s ac failure 4, 7, and 8 detection time bus normal mode t ac478d 0.75 ? 4.0 ms notes 10. cyclic sense and forced wake-up timing accuracy are based on the sleep m ode oscillator tolerance. 11. no overlap between two adjacent thresholds. table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33389 electrical characteristics dynamic electrical characteristics bus transmitter (continued) ac failure 4, 7, and 8 recovery time bus normal mode t ac478r 10 ? 60 s ac failure 3, 4, and 7 detection time bus stand-by mode, v bat = 12 v t ac347d 0.8 ? 8.0 ms ac failure 3, 4 and 7 recovery time bus stand-by mode, v bat = 12 v t ac347r ? 2.5 ? ms ac edge count difference between canh/canl for failures 1, 2, 5 detection bus normal mode can 125d ? 3.0 ? ? ac edge count difference between canh/canl for failures 1, 2, 5 recovery bus normal mode can 125r ? 3.0 ? ? tx permanent dominant timer disable time bus normal and failure modes t txd 0.75 ? 4.0 ms power input timing v1 reset delay time t d 2.0 ? 20 s v1 line regulation 9.0 v < v bat < 16.5, i load = 10 ma t d -15 2.0 +15 mv v1 line regulation 5.5 v < v bat < 27 v i load = 10 ma t d -50 10 +50 mv v1 load regulation 1.0 ma < i load < 100 ma t d -50 ? +50 mv v1 line ripple rejection 100 hz, 1.0 v pp on v bat = 12 v, i load = 100 ma (12) t d 30 55 ? db v1 line transient response v bat from 12 v to 40 v in 1.0 s, (10 f, esr = 3 ?) t d ? 27 ? mv v1 load transient response i load from 10 a to 100 ma in 1.0 s (cload = 10 f, esr = 3 ? ) (13) t d ? 400 ? mv v1 load transient response i load from 10 a to 100 ma in 1.0 s (cload = 10 f, esr= 0.1 ? ) t d ? 16 ? mv notes 12. guaranteed by design. not production tested. 13. this condition does not produce a reset table 5. dynamic electrical characteristics (continued) characteristics noted under conditions 7.0 v v sup 18 v, - 40 c t a 125 c, gnd = 0 v unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. characteristic symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 33389 electrical characteristics timing diagrams timing diagrams figure 4. input timing switch characteristics si sclk cs don?t care don?t care don?t care valid valid t lead t wsclkh t wsclkl t r t f t lag t sisu t si(hold)
analog integrated circuit device data freescale semiconductor 17 33389 functional description introduction functional description introduction the system basis chip (sbc) is an integrated circuit dedicated to car body applications. it includes three main blocks: 1. a dual voltage regulator 2. reset, watchdog, wake-up inputs, cyclic wake-up 3. can low speed fault tolerant physical interface supplies two low drop regulators and one switch to v bat are provided to supply the ecu microcontroller or peripherals, with independent control and monitoring through spi. functional pin description transmit and receive data (tx and rx) the rx and tx pins (receive data and transmit data pins, respectively) are connected to a microcontroller?s can protocol handler. tx is an input and controls the canh and canl line state (dominant when tx is low, recessive when tx is high). rx is an output and reports the bus state. voltage regulator one and two (v1 and v2) the v1 pin is a 3% low drop voltage regulator dedicated to the microcontroller supply (nominal 5v supply). the v2 pin is a low drop volt age regulator dedicated to the peripherals supply (nominal 5v supply). reset ( rst ) the rst (reset) pin is an input/output pin. the typical reset duration from sbc to microcontroller is 1ms. if longer times are required, an external capacitor can be used. sbc provides two rst output pull-up currents. a typical 30 a pull up when vreset is below 2.5v and a 300ua pull up when reset voltage is higher than 2.5v. rst is also an input for the sbc. it means the mc33389 is forced to normal request mode after rst is released by the microcontroller interrupt ( int ) the interrupt pin int is an output that is set low when an interrupt occurs. int is enabled using the interrupt register (intr). when an interrupt occurs, int stays low until the interrupt source is cleared. int output also reports a wake-up event. ground (gnd) this pin is the ground of the integrated circuit. master in/ slave out (miso) miso is the master in slave out pin of the serial peripheral interface. data is sent from the sbc to the microcontroller through the miso pin. master out/ slave in (mosi) mosi is the master out slave in pin of the serial peripheral interface. control data from a microcontroller is received through this pin. system clock (sclk) this pin clocks the internal shift registers for spi communication. chip select ( cs ) cs is the chip select pin of the serial peripheral interface (spi). when this pin is low, the spi port of the device is selected. level 0-2 inputs (l0: l2) the l0: l2 pins can be connected to contact switches or the output of other ics for external inputs. the input states can be read by the spi. these inputs can be used as wake- up events for the sbc. no connect (nc) no pin connection. termination resistance (high and low?) (rth and rtl) external can bus high and low termination resistance pins are connected to these pins. can high and can low outputs (canh and canl) the can high and can low pins are the interfaces to the can bus lines. they are controll ed by tx input level, and the state of canh and canl is reported through rx output. voltage battery (vbat) this pin is the voltage su pply from the battery. voltage regulator three (v3) this pin is a 10 ? switch to vbat, which is used to supply external contacts or relays.
analog integrated circuit device data 18 freescale semiconductor 33389 functional device operation functional device operation voltage regulator v1 v1 is a 5.0 v, three percent low drop voltage regulator dedicated to the microcontroller supply. it can deliver up to 100 ma. it is totally protected against short-to-ground (current limitation) and over temperature. v1 is active in normal request, normal, and stand-by modes. no forward parasitic diode exists from v1 to v bat . this means if v bat voltage drops below v1, high current flowing from v1 to v bat will not discharge the capacitor connected to v1. its stored energy will only be used to supply the microcontroller and gives time to save all relevant data. ? under voltage reset?v1 is monitored for under voltage (power-up, power down) and a reset is provided at rst output for 1 ms. this ensures proper initialization of the microcontroller at power-on or after supply is lost. furthermore, a flag is set in the reset source register (rsr) and can be read via the spi. ? over temperature protecti on?v1 internal ballast transistor is monitored for ov er temperature. two detection thresholds are provided. a pr e-warning threshold at 145c and a shut-off threshold at 175c. once the first threshold is reached, a flag is set in the over temperature status register (otsr). a maskable in terrupt can be sent to the microcontroller. once the second threshold is reached, a flag is set in the otsr, a mask able interrupt is sent to the microcontroller and v1 is switched off. once the junction temperature is back to the pre-warning threshold, v1 regulator will be automatically switched on. note: current capability of v1, v2 and v3 depends upon the thermal management. over temperature shutdown might be reached and lead to turn off of v1, v2, and v3 for output current below their maximum current capability. voltage regulator v2 v2 is a 5.0 v low drop voltage regulator dedicated to peripherals supply. it can del iver up to 200 ma and is protected against short to ground (current limitation) and over temperature. v2 is active in normal mode. ? under voltage detection?v2 is monitored for under voltage and a flag is set in the voltage supply status register (vssr). ? over temperature protecti on?v2 internal ballast transistor is monitored for ov ertemperature. two detection thresholds are provided. a pre-warning threshold at 140c and a shut-off threshold at 165c. once the first threshold is reached, a flag is set in the readable otsr register. a maskable interrupt can be sent to microcontroller. once the second threshold is reached, a flag is set in the otsr register, v2 is switched off. it can only be switched on again via the spi. switch v3 v3 is a 10 ? switch to v bat . it can be used to supply external contacts or relays. a great flexibility is given for the different possible ways for its cont rol. it is protected against short to ground (current limitation). ? over temperature protection ?v3 output transistor is monitored for over temperature. once the threshold is reached, a flag is set in the vssr register, v3 is switched off. it will be automatically switched on once the junction temperature is back to the pre-warning threshold. table 6. v1 control conditions for v1 on conditions for v1 off normal request mode (at v1 power on) sleep mode (via spi) normal mode (via spi) shut-off temperature threshold reached stand-by mode (via spi) no v bat power supply (cold start) v1 below pre-warning temperature threshold emergency mode during rest ? table 7. v2 control conditions for v2 on conditions for v2 off normal mode (via spi) and v2 below shut-off temperature threshold sleep, stand-by, normal request, or emergency modes (via spi) ? shut-off temperature threshold reached ? v1 disabled (for any reason) table 8. v3 control conditions for v3 on conditions for v3 off permanently in normal mode if configured via spi permanently in normal mode if configured permanently in stand-by mode if configured via spi normal request mode in sleep mode, during enable time of cyclic sense if configured permanently in stand-by mode if configured ? permanently in sleep mode if configured
analog integrated circuit device data freescale semiconductor 19 33389 functional device operation supply and v bat block ? v bat monitoring?v bat is the main power supply coming from the battery voltage after an external protection diode (for reverse battery). v bat is monitored for under voltage and over voltage. ? v bat under voltage?v bat is monitored for under voltage if it is below 4.0 v the ba tfail flag is se t in the vssr register and a maskable interrupt is sent to the microcontroller. ? v bat over voltage? when v bat is > 20 v, the bathigh flag is set in the vssr regist er. a maskable interrupt is sent to the microcontroller. no specific action is taken to reduce current consumption (to limit power dissipation). this is to allow the entire flexib ility to the microcontroller for a decision. can transceiver the device incorporates a low speed 125 kbaud can physical interface. its electrical parameters for the canl, canh, rtl,rth, rx, and tx pins are identical to the 33388, stand alone can physical interface. the mode control for the can transceiver (normal, v bat stand-by, sleep, etc.) are select able through the 33389 spi interface. ? baud rate up to 125 kbit/s ? supports unshielded bus wires ? short-circuit proof to battery and ground in 12 v powered systems ? supports single-wire transmission modes with ground offset voltages up to 1.5 v ? automatic switching to single wire mode in case of bus failures ? automatic reset to differential mode if bus failure is removed ? low electromagnetic interference (emi) due to built-in slope control and signal symmetry ? fully integrated receiver filters ? thermally protected ? bus lines protected against automotive transients ? low current bus stand-by mode with wake-up capability via the bus ? an unpowered node does not disturb the bus lines figure 5. can simpli fied block diagram consequence of failure detections s1 is the switch from rth to ground s2 is the switch from rtl to v2 and s3 is the switch from rtl to v bat each failure type provides dat a concerning which switch is open and which driver is disabled. failure 1: nothing done failure 2: nothing done failure3: s1 open. driver canh is disabled failure4: s2 and s3 open. driver canl is disabled failure5: nothing done failure6: s2 and s3 open. driver canl disabled failure7: s2 and s3 open. driver canl disabled failure8: s1 open. canh driver disable can transceiver description the can transceiver is an interface between can protocol controller and the physical bus. it is intended for low ? in sleep mode, during disable time of cyclic sense if configured ? over temp threshold reached ? v1 disabled (for any reason) ? v2 over temperature shutdown table 8. v3 control termination protection rx tx can_h can_l rth rtl v dd2 spi transmitter receiver - fail detect - receive mode v dd2 v bat can transceiver register drivers can transceiver simplified block diagram 12.5k s3 s2 s1 v dd bat rtl canh canl rth
analog integrated circuit device data 20 freescale semiconductor 33389 functional device operation speed applications up to 125 kbit/s in passenger cars. it provides differential transmission capability, but will switch in error condition to single wire transmitter and/or receiver. the rise and fall slopes are limited to reduce radio frequency interference (rfi). this provides use of an unshielded twisted pair or a para llel pair of wires for the bus. it supports transmission capability on either bus wire if one of the bus wire is corrupted. the logic failure detection automatically selects a suitable transmission mode. in a normal operation (no wiring failures), the differential bus state is the output to rx. t he differential receiver inputs are connected to canh and canl through integrated filters. the filtered inputs signals are also used for the single wire receivers. the canh and canl receivers have threshold voltages, assuring maximum no ise margin in single wire modes. in the rx only mode, the transmitter is disabled; however, the receive pa rt of the transceiver remains active. in this mode, rx reports bus and tx activity ( rx = tx or bus dominant). failure detection and management is the same as the bus normal mode. failure detector the failure detector is active in rxtx and rx only operation modes. the detector recognizes the following single bus failures and switc hes to an appropriate mode. 1. canh wire interrupted 2. canl wire interrupted or shorted to 5.0 v 3. canh short-circuit to battery 4. canl short-circuit to ground 5. canh short-circuit to ground 6. canl short-circuit to battery 7. canl mutually shorted to canh 8. canh to v2 (5.0 v) note: shorts-circuit failures are detected for 0 to 50 ? shorts. the differential receiver (canh-canl) threshold is set at -2.8 v, this assures a proper reception in the normal operating modes. in case of failures 1, 2, and 5 the on-going message is not destroyed due to noise margin. failures 3 and 6 are detected by comparators respectively connected to canh and canl. if the comparator threshold is exceeded for a certain time (t ac3d , t ac6d ), the reception is switched to single wire mode. this time is required to avoid false triggering by external rf fields. recovery from these failures is detected automatically after a certain (t ac3r , t ac6r ) time-out (filtering). failures 4 and 7 initially result in a permanent dominant level at rx. after a time-out, the canl driver and the rtl pins are switched off. only a weak pull-up at canl remains. reception continues by switching to single wire mode through canh. when failures 4 or 7 are removed, the recessive bus levels are restored. if the differential voltage remains below the recessive threshold for a certain (t ac478r ) time, reception and transmission switch back to the differential mode. if any of the eight wiring failure occurs, a flag is set in the tesrh and tesrl status registers. eight different types of errors are distinguished out of these eight errors. they are separately stored in these register. please refer to the tables 35 and 36 . a maskable interrupt is sent to the microcontroller. on error recovery, the corresponding flag is reset after read-out operation. during all single wire transmissions, the emc performance (both immunity and emission) is worse than in the differential mode. integrated receiver fi lters suppress any high frequency noise induced into the bus wires. the cut-off frequency of these filters is a compromise between propagation delay and high frequency suppression. in the single wire mode, low frequency noise can not be distinguished from the expected signal. in the event of a permanent dominant tx state (for more than 2.0 ms) the output drivers are disabled. that assures the operation of the complete syst em in case of a permanent dominant tx state of one control unit. the can interface of a defective ecu, which has tx permanently low, will automatically be set to the receive only mode and therefore will not lock the complete can bus. protection a current limiting circuit protects the transmitter output stages against short-circuit to positive and negative battery voltage. if the junction te mperature exceeds a maximum value, the transmitter output stages are disabled. because the transmitter is responsible for a part of the power dissipation, this results in a reduced power dissipation resulting in a lower chip temper ature. all other parts of the transceiver will remain operating. the canh and canl inputs are protected against electrical transients, and may occur in an automotive environment. thermal management the 33389 is proposed in two different packages: 1. hsop-20 for high power applications 2. so28wb with eight pins to the lead frame for medium power applications hsop20 package for such a package, the heat flow is mainly vertical and each heat source (dissipating element) can be seen as an independent thermal resistance to the heatsink. the thermal network can be roughly depicted in figure 6 .
analog integrated circuit device data freescale semiconductor 21 33389 functional device operation figure 6. hsop-20 simplified thermal model example assuming i v1 = 100 ma at v bat = 16 v, i v2 =150 ma at v bat = 16 v (excluding can consumption). i can = 50 ma at v bat =16 v, we have: p v1 = 1. 1 w, p v2 = 1.65 w, p can = 0.55 w system assumptions: if t amb = 85c and r thc/a = 18c/w, this gives: t case = t amb +r thc/a x 3.3 w = 85 + 18 x 3.3 = 145c and t j v1 = t j v2 = t jcan =155c. this example represents the limit for the maximum power dissipation with a hsop20. so28wb package the case (pin) to junction r th is represented here by only one thermal resistance for the total power because the three power sources strongly interact on the silicon for such a package. figure 7. so28wb simplified thermal model example assuming i v1 = 45 ma at v bat = 16 v, i v2 = 45 ma at v bat = 16 v (excluding can consumption). i can = 50 ma at v bat = 16 v, we have: p v1 = 0.5 w, p v2 =0.5 w, p can =0.55 w thus p total =1.55w system assumptions: if t amb = 85c and r thc/a = 25c/w, this gives: t case = t amb + r thc/a x 1.55 w = 85+25 x 1.55 = 124c and t j v1 = 124 + 20 x 1.55 = 155c. different device versions the mc33389 is proposed in several package versions, and also offers slight differen ces in term of functionalities. the device version is identified in the device part number by the first letter after the 389 number. the package identification is done by the last two letters of the part number (dw for so28 wide body, dh for power so20). t ambient t case (heatsink) v1 power v2 power can power t j (max 155c ) r thj/c =18c/w 6.5c/w 9c/w r thc/a (ecu supplier dependent) t case (pin) t j (max 155c) total power r thc/a t ambient r thj/c = 20c/w
analog integrated circuit device data 22 freescale semiconductor 33389 functional device operation operational modes operational modes can transceiver modes the can transceiver has its own functioning modes: rxtx mode, term v bat /term v cc mode, and rx only mode. they are controlled by t he transceiver control/status register (tcr). ? rxtx mode?full transmitting and receiving capabilities are enabled. full failure detection is enabled. note: standard/rxtx and extended/rxtx are equivalent. ? rx only mode?the transmitter is disabled but the receive portion of the transceiver remains active. in this mode, rx reports bus and tx activity ( rx = tx or bus dominant). note: standard/rx only and extended/rx only are equivalent. ? bus stand-by mode?is the low power mode for the can transceiver. the driver and receivers are disabled. wake- up capability on both bus lines as well as failure 3, 4, 7, and 8 detection are enabled. rtl termination is set to v bat in the bus stand-by mode. low power modes the transceiver provides a low power mode, entered and exited by a spi command. this is the bus stand-by mode having the lowest power consum ption for the transceiver. canl is biased to the battery voltage via the rtl output and the pull-up current source on canl and pull down current source on canh are disabled. wake-up requests are recognized by the transceiver when a dominant state is detected on either bus wake-up lines. on a bus wake-up request, the sbc will activate the int output or, if it is in the sleep mode, switch to the normal request mode. this event is stored in the wake-up input status register (wuisr). to prevent a false wake-up resulting from transients or (rf) fields, wake-up threshold levels have to be maintained for a certain time. while in t he transceiver low power mode, failure detection circuit remains partly active preventing increased power consumption in cases of error 3, 4, 7, and 8. power-on after the vbat supply is switched on, the sbc is in normal request mode. bus stand-by is the corresponding mode for the can transceiver. the can transceiver is supplied by v2. as long as v2 is below its under voltage threshold, the transceiver is forced to bus stand-by mode (fail safe property). sbc modes global power save concept the sbc minimizes power consumption of the ecu. several operating modes are available to go to low power consumption when the full activity is not required. several possibilities are provided to wake-up the ecu. this permits peripherals or the microcontroller to be switched off when no activity on the ecu is required. two switchable independent supply voltages (v1 and v2) are provided for optimum ecu power management. generalities the sbc can be operated in four modes: 1. sleep 2. stand-by 3. normal 4. emergency after reset, the 33389 is automatically initialized to the temporary mode, normal request, while waiting for microcontroller configuration. reset mode this mode is entered after sbc power-up, or if an incorrect software watchdog trigger occurs. the minimum duration for reset mode is 1.0 ms typical, and unless there is a v1 failure condition, the sbc enters the normal request mode after reset. in the case of a v1 failure condition leading to v1 low (ex: short to ground), the sbc switches to the reset mode. if v1 is still below the reset threshold after 100 ms, the behavior depends upon the device version a or c: ? c version: the 33389cdw and the 33389cdh will remain in the reset mode. ? d version: the 33389ddw and the 33389deg will remain in the reset mode. note that the reset mode threshold for the d version is slightly higher than the c version. normal request mode the normal request mode is the default mode after 33389 reset. v1 is active, while v2 and v3 are passive. the sbc is not configured. the default values are set in the registers. the sbc awaits data configuration via the spi. if no spi data is received 75 ms after the reset is released, the sbc switches itself into the sleep mode. the software timing word (in swcr) provides the data the sbc must receive to consider when the microcontroller begins the configuration sequ ence. once received, this software timing word, and the watchdog timer, become active. any other control data can then be sent from the microcontroller to sbc. the watchdog is not active in the normal request mode before the software timing word is programmed into the sbc. in this mode, neither v2 nor the can transmitter are active.
analog integrated circuit device data freescale semiconductor 23 33389 functional device operation operational modes sbc normal mode in this mode, v1 and v2 are active, v3 can be set active or passive via the spi. therefore, the whole ecu can be operated. normal mode is entered by a swcr configuration in the normal request mode. sbc stand-by mode in this mode v1 is active and v2 is passive. v3 can be either permanently active or permanently passive. this is a low power mode with v1 active in order to have a fast reaction time in case of any wake-up. for stand-by mode, the s bus circuit (sbc) monitors the software. it means the microcontroller runs, is monitored, and must serve as a watchdog trigger. s bus circuit sleep mode this is a low power consumption mode. v1 and v2 are disabled. v3 can be permanently disabled or cyclically active. emergency mode in case the microcontroller de tects the ecu or the system is no longer under control, it may decide to switch the sbc to the emergency mode. v1, v2, and v3 become passive and wake-ups are not detected. the only way to leave this mode is to disconnect the ecu from the battery voltage (batfail detection). table 9. normal request: v1 active and v2/v3 passive entering normal request leaving normal request sbc reset just released when first receiving the sw timing word, sbc goes to normal ? if time-out without receiving spi commands (75ms), sbc goes to seep table 10. sbc normal mode: v1/v2 active while v3 is active or passive entering normal mode leaving normal mode by spi command by spi command, going to any other mode after swcr register configuration in normal request mode watchdog time-out, going to normal request after activat - ing reset ? v1 undervoltage detection, going to normal request mode after activating reset table 11. stand-by: v1 active, v2 passive, v3 active or passive, watchdog is active entering stand-by leaving stand-by ? if sw timeout going to normal request after microcontroller reset by spi command by spi command going to any other mode ? v1 under voltage detection, going to normal request mode after activating reset ? external activation of the rst pin table 12. sbc sleep mode: v1/v2 are passive, v3 is passive or cyclic entering sleep mode leaving sleep mode if sw timing not configured 75 ms after entering normal request mode can wake-up, going to normal request by spi command if a wake-up is detected with cyclic sense for 33389adw only: if v1 is below v1 reset for more than 100 ms if a wake-up is detected with wake-up not connected to v3 (permanent sense) ? forced wake-up (see forced wake-up section ) ? spi wake-up (see wake-up by spi section) table 13. sbc emergency mode: v1:v3 are passive entering emergency mode leaving emergency mode by spi command sbc batfail detection (discon - nection of the battery voltage) table 11. stand-by: v1 acti ve, v2 passive, v3 active or passive, watchdog is active entering stand-by leaving stand-by
analog integrated circuit device data 24 freescale semiconductor 33389 functional device operation operational modes figure 8. typical behavior at power-on note: in the normal request mode, if a spi command is received before the software timing configuration (swcr register), it will not be taken in to account by the sbc (except for the go-to emergency mode). correspondence between sbc and can transceiver modes table 14 provides different possible can transceiver modes versus sbc modes. watchdog the software window watchdog function monitors the microcontroller operation in the normal and stand-by modes. the window watchdog timing is derived from the sbc clock. the desired watchdog timing must be first transmitted during the sbc configuration, in the normal request mode, via spi to swcr. it can also be changed later on. selectable watchdog timings are 5.0 ms, 10 ms, 20 ms, 33 ms, 50 ms, 75 ms, 100 ms and 200 ms. these timings correspond to the full disable window plus full enable window. figure 9. window watchdog timing as soon as the watchdog trig ger is received in the enable window, the internal counter is reset and begins a new disable window. the sbc triggers the watchdog word at cs low-to-high transition. any watchdog trigger outside the enable window leads to an sbc reset. ? normal and stand-by modes? the sbc get the watchdog word from the microcontroller via spi in the normal mode. in case of a trigger time failure (no trigger or trigger outside the enable window) the sbc reset is switched to active. ? normal request, sleep, and emergency mode? watchdog is not active in these modes. wake-up capabilities several wake-up capabilities are available. forced wake-up the forced wake-up is enabled and disabled by spi in the v3 register. it is used to au tomatically wake- up the system by supplying v1 with proper reset in the sleep mode. this corresponds to jump into th e normal request mode. if the sbc is not properly configured within 75 ms, it switches back to the sleep mode until the nex t wake-up. if both cyclic sense and forced wake-up are enabled by the spi while in the sleep mode, only cyclic sense is active. the period of forced wake-up are 32 ms, 64 ms, 128 ms, 256 ms, 512 ms, 1024 ms, 2048 ms, and 8192 ms chosen by spi in the cyclic timing control register (cytcr). wake-up inputs (local wake-up)/cyclic sense sbc provides three wake-up inputs to monitor external events such as closing/openin g of switches. the wake-up feature is available in norma l, stand-by, and sleep modes. table 14. can modes vs. sbc modes when sbc is in the following mode can transceiver can be in reset condition bus stand-by mode normal request bus stand-by mode normal rxtx or rxonly or busstand-by stand-by bus stand-by sleep bus stand-by emergency bus stand-by normal and v2 off (over load) in case v2 is turned off either by spi command (stand-by mode) or by the sbc itself due to v2 over load condition (v2 short to ground or v2 over tem - perature) the can is automati - cally set into the bus stand-by mode and does not return to txrx mode automatically when v2 is back to 5.0 v. the can must be re configured to txrx or rx only mode after a v2 turn off bus stand-by ecu connected to battery reset v1 low normal sleep normal v1 on spi sw timing configuration at t<75ms no spi sw timing configuration at t=75ms ( reset released ) emergency spi go to emergency at t<75ms request watchdog trigger sbc watchdog window earliest trigger time latest disabled window nom. trigger period time out latest sbc-reset out 50% 50% watchdog timing enable window reset trigger time time
analog integrated circuit device data freescale semiconductor 25 33389 functional device operation operational modes the switches can be directly connected to v bat or to v3. the sbc must be properly configured by setting the bit wi2v3 in the v3 register. in this case, wake-ups are only detected when v3 is on. it can take advantage of the v3 cyclic sense feature. if both cyclic sense and forced wake-up are enabled by the spi in the sleep mode, only cyclic sense will be active. options for wake input different conditions for wake-up can be chosen for wake- up input pins (via spi in the wake-up input control register (wuicr). ? no wake-up? wake-ups are not detected whatever occurs on wake-up inputs. ? high-state?if the input pin vo ltage is above the detection threshold during more than a 20 s filter time, a wake-up is detected. a flag is set in the wuisr. ? low-state?if the input pin vo ltage is below the detection threshold during more than a 20 s filter time, a wake-up is detected. a flag is set in the wuisr. ? change of state?each change of the wake-up input pin is considered as a wake-up if it lasts more than a 20 s filter time. the first reference state (no wake-up) is the wake-up input state when the sbc is pr ogrammed to this option. a flag is set in the wuisr. ? multiple sampling events?when wake-up inputs are used with v3 in cyclic sense in the sleep mode. for positive edge sensitivity, two samples low followed by two samples high are necessary to validate the wake-up condition. for negative edge sensitivity, two samples high followed by two samples low are necessary to validate the wake-up condition. for both edge sensitivity, two samples at a given state followed by two samples in the opposite state are necessary to validate the wake-up condition. wake-up inputs with cyclic sense connecting the external switches to v3 allows power saving because v3 can be programmed to be active, passive, or cyclic (cyclic sense). this provides great flexibility reducing total power consumption while allowing full wake-up capabilities. cyclic sense is available only in the sleep mode. the period of the cyclic sense can be chosen out of eight different timings: 32 ms, 64 ms, 128 ms, 256 ms, 512 ms, 1024 ms, 2048 ms, and 8192 ms programmable via spi in the cytcr register. once acti vated, v3 remains on during 400 s. the wake-up inputs states are sampled at 300 s. figure 10. v3 timing note: in sleep mode, the cyclic sense feature ?exclusive or? the forced wake-up is chosen (not both). figure 11. cyclic sense timing wake-up inputs with permanent sense wake-up detection can also be accomplished in a permanent way in normal and stand-by modes. if the contacts are connected to v3, wake-ups are only detected if v3 is on. wake-ups are also detected in a permanent way in the sleep mode if the contacts are directly connected to v bat (if they are connected to v3, only cyclic sense is available in sleep mode). 300 s 400 s v3 passive active cyclic sense programmable period wake-up inputs sample point 1 1 1 0 0 0 0 1 1 actual state (read) memory state int (wake-up active = 0) 0 80 ms 160 ms v3 wake-up switch status v(l1) read l1 int (t0) (t1) open closed read setup 400 s 300 s sample point (80%) cyclic sense connected to wake-up inputs. example: with wake-up input l1 sensitivity to low state and timing = 80 ms
analog integrated circuit device data 26 freescale semiconductor 33389 functional device operation operational modes local wake-up consequences in normal or stand-by modes, the real time state of each wake-up input pin is stored in the readable wake-up input control register (wuirti). wake-ups are detected according to the selected option. a flag is set in the wuisr. a maskable interrupt is then sent via int output. in the sleep mode, a local wake-up leads to a jump to normal request mode (via proper reset of the microcontroller). a flag is set in the wuisr. wake-up by spi in some applications, the microcontroller might be supplied by an external v dd , remaining powered in sbc sleep mode. in this case, a feature is provided making possible to wake-up the sbc by spi activity. after v1 is totally switched off in the sleep mode (v1< 1.5 v), if a falling edge occurs on cs (crossing 2.5 v threshold), a wake-up by spi is detected, the sbc switches to the normal request mode. a flag is set in isr2. interrupt output the int output may be activated in the following cases: ?v bat overvoltage (bathigh) ?v bat undervoltage (batfail) ? high temperature on v1 or v2 ? pre-warning temperature on v1 or v2 ? can bus failure ? spi error ? local wake-up (can be used for low battery detection) ? bus wake-up all these interrupts are maskable. please see the spi registers descriptions on page 34 . reset input/output the reset ( rst ) pin is an input/output pin. the typical reset duration from sbc to microcontroller is 1 ms. if extended times are required, an external capacitor can be used. sbc provides two rst output pull-up currents. a typical 30 a pull up when vreset is below 2.5 v and a 300 a pull up when reset voltage is higher than 2.5 v. rst is also an input for the sbc. it means the 33389 is forced to the normal request mode after rst is released by the microcontroller. ground shift detection when normally working in a two-wire operating mode, the can transmission can afford some ground shift between different nodes without trouble. ne vertheless, in case of bus failure, the transceiver switches to single-wire operation, therefore working with less noise margin. the affordable ground shift is decreased in this case. the sbc is provided with a ground shift detection for diagnosis purpose. four ground shift levels (gsl) are selectable and the detection is stored in the gsl register, accessible via the spi. detection principle the ground shift to detect is se lected via the spi from four different values (-0.7 v, -1.2 v, -1.7 v, -2.2 v). the canh voltage is sensed at each tx falling edge (end of recessive state). if it is detected to be below the selected ground shift threshold, the bit shift is set at one in the gsl register. no filter is implemented. required filtering for reliable detection should be achieved by software (e.g. several trials). figure 12. sbc operation mode table 15. sbc mode vs. local wake-up behavior sbc modes local wake-up behaviour normal request no detection normal and stand-by detection active according to the option. the event is stored in wuisr. the sbc may activate int output. real time state of each wake-up input pin available in wuirti register sleep detection active according to the option. the event is stored in wuisr. the sbc switches to normal request mode emergency no detection mode v1 & v2 regulators, v3 switch wake-up capabilities (if enabled) reset pin (rst) interrupt pin int software watchdog can cell reset state v1: on (unless failure condition) v2: off v3:off ? low (duration 1 ms) ? ? term v bat normal request v1: on (75 ms timeout) v2: off v3: off ? high (active low -go to reset state if v1 under voltage occurs) ? ? term v bat
analog integrated circuit device data freescale semiconductor 27 33389 functional device operation operational modes figure 13. state machine normal v1: on v2: on v3: on/off ? high (active low -go to reset state if w/d or v1 under voltage occurs) if enabled, signal failure condition or l0, l1, l2 inputs state change running tx/rx, or rx only, or term v bat stand-by v1: on v2: off v3: on/off ? same as normal mode same as normal mode running term v bat sleep v1: off v2: off v3: off/cyclic ?can ? spi ? l0,l1,l2 ? cyclic sense ? forced wake- up low not active not running term v bat + wake- up capability emergency v1: off v2: off v3: off none low not active not running term v bat mode v1 & v2 regulators, v3 switch wake-up capabilities (if enabled) reset pin (rst) interrupt pin int software watchdog can cell power down reset normal request stand-by normal sleep reset counter (1 ms) expired and v1 high (2) sbc power-up v1low (1) wake-up (8) spi: stand-by (7) spi: normal (6) spi: sleep (5) sp i: slee p (5) w/d: trigger ( 3) w/d: time-out (4) or v1low (1) w/d: time-out (4) or v1low (1) 75 ms timeout expired emergency spi: emergency spi: emergency 33389 c version (9b)
analog integrated circuit device data 28 freescale semiconductor 33389 functional device operation operational modes figure 14. state machine legend 1. v1 low = v1 below reset threshold 2. v1 high = v1 above reset threshold 3. w/d: trigger = scwr register writ e operation during normal request mode 4. w/d: time-out = swcr register not written before w/d time-out period expired, or w/d written in incorrect time window. in normal request mode time out is 75ms 5. spi: sleep = spi write command to mcr and mcvr registers, data sleep 6. spi: normal = spi write command to mcr and mcvr registers, data normal 7. spi: stand-by = spi write command to mcr and mcvr registers, data stand-by 8. wake-up = one of the following events occur: can wake-up, forced wake-up, cyclic sens e wake-up, direct lx wake- up, or spi cs wake-up 9. v1low > 100 ms = v1 below reset threshold for more than 100 ms a. this condition leads to sbc in sleep mode only for the 33389adw (so28 package) b. v1 low for > 100 ms does not lead to sleep mode for the 33389cdw (so28wb package) and for the 33389cdh (hsop20 package)
analog integrated circuit device data freescale semiconductor 29 33389 functional device operation operational modes sleep mode activation once in the sleep mode, the sbc turns the v1 and v2 regulator off . thus the microcontroller can not run any mode. in order to have the microcontroller run again, the sbc should enable and turn on v1. this is achieved by an sbc wake-up event. several options are available to wake-up the sbc and the application and have the microcontroller in run mode. some wake-ups are selectable; some are always active in sleep mode: ? wake-up from can interface and wake-up from spi ( cs ) are always active. ? wake-up from l0,l1, and l2 inputs, with and without cyclic sense and the forced wake-up (fwu) are selectable. the selection must be done while the sbc is in normal or stand-by mode, and prior to enter sleep mode. general condition to enter sleep mode all previous wake-up conditions must be cleared, assuring the sbc enters the sleep mode, and write operations into the mcr and mcvr. to clear a wake-up condition requires reading the appropriate register. once the sbc has powered-up from zero (battery power- up or cold start), the following registers must be read: ? wuicr?possible wake-up event report from can bus ? rsr?report a v1 under voltage ? vssr?reports a v bat fail flag once these read operations are completed, the wake-up conditions, or flags are reset. the vbsr0 bit in the vssr c an be used to determine if the sbc has experienced a loss of battery voltage. once the sbc is awakened from sleep mode the following registers indicate the wake-up source. they must be cleared to allow the sbc to enter sleep mode again: ? wuicr?wake-up event report for can or spi buses ? wuisr? wake-up event report for the l0,l1, and l2 inputs ? rsr?report a v1 under voltage ? vssr?reports a v bat fail flag ?etc. the ensuing paragraphs describe the write operation to be accomplished for the several sleep modes and wake-up control options. in addition to fwu, cyclic sense and direct wake-up, the can and spi wake will always be activated. sleep mode with can and spi wake-up to enter the sleep mode and activate the only can or spi wake-up, there is no dedicated wake-up condition to be completed. the sbc has can and spi wake-up sources always active in the sleep mode. to enter the sleep mode in this case, while the sbc is in normal or stand-by mode: ? write to v3r?data 0000 (this clears the wi2v3 bit, is set to1after reset) ? write to mcr?data sleep (100) ? write to mcvr?data sleep (100) the sbc then enters the sleep mode. sleep mode enter wi th forced wake-up to enter the sleep mode and activate the forced wake-up, write to the following registers: ? write to v3r (data 0100) this set the fwu bit to 1 ? write the desired wake-up time to cytcr. (this sets the time the sbc will stay in the sleep mode). ? write to mcr?data sleep (100) ? write to mcvr? data sleep (100) the sbc then enters the sleep mode. it will wake-up after the time period is selected in the cytcr. sleep mode enter wi th cyclic sense to enter the sleep mode a nd activate the cyclic sense wake-up the following registers must be written: ? write to v3r (data 1010) this sets the vi2v3 and cys bits to 1 ? write to cytcr the desired cyclic sense period. (this sets the time the sbc will wait in the sleep mode to turn on v3 and sense the lx inputs) ? write to wuicr bits 0 and 1 to select the edge sensitivity for the lx inputs ? write to mcr?data sleep (100) ? write to mcvr?data sleep (100) the sbc then enters the sleep mode. it will periodically turn on v3 and while v3 is on, sample the level of the ls inputs. if any of the 3 lx inputs is in the correct state for two consecutive samples, sbc will wake-up. if not, it will stay in the sleep mode. refer to device description for detail. sleep mode enter with di rect lx input wake-up to enter the sleep mode and activate the direct wake-up from the lx inputs, the following registers must be written: ? write to v3r (data 0000) this clear vi2v3 bit ? write to wuicr bits 0 and 1 to select the edge sensitivity for the lx inputs ? write to mcr?data sleep (100) ? write to mcvr?data sleep (100) the sbc then enters the sleep mode. it will wake-up as soon as any of the lx input read the correct state.
analog integrated circuit device data 30 freescale semiconductor 33389 functional device operation logic commands and registers figure 15. current vs temp and batt voltage logic commands and registers spi introduction this spi system is flexible enough to communicate directly with numerous standard peripher als and mcus available from motorola and other semiconductor manufacturers. spi reduces the number of pins necessary for input/output on the 33389. the spi system of comm unication consis ts of the mcu transmitting, and in return, receiving one data bit of information per clock cycle. da ta bits of information are simultaneously transmitted by one pin, microcontroller out serial in (mosi), and received by another pin, microcontroller in serial out (miso), of the mcu. figure 16 illustrates the basic spi configuration between an mcu and one 33389. the spi serial operation is guaranteed to 2.0 mhz. figure 16. spi interface with microcontroller cs pin the system mcu selects the mc33389 to be communicated with, thr ough the use of the cs pin. whenever the pin is in logic low state, da ta can be transferred from the mcu to the mc33389 and vice versa. clocked-in data from the mcu is transferred from the mc33389 shift register and latched into the addressed registers on the rising edge of the cs signal if the read/write bit is set and the parity check was successful. the cs pin controls the output driv er of the serial output pin. whenever the cs pin goes to a logic low state, the miso pin output driver is enabled allowing information to be transferred from the mc33389 to the mcu. to avoid any spurious data, it is essential t hat the high-to-low transition of the cs signal occur only when sclk is in a logic low state. sclk pin the system clock pin (sclk) clocks the internal shift registers of the mc33389. the serial input pin (mosi) accepts data into the input shift register on the falling edge of the sclk signal while the serial output pin (miso) shifts data information out of the shift register on the rising edge of the sclk signal. false clocking of the shift register must be avoided to guarantee validity of data. it is essential that the sclk pin be in a logic low stat e whenever chip select bar pin ( cs ) makes any transition. for this reason, it is recommended though not necessary, that the sclk pin be kept in a low logic state as long as the device is not accessed ( cs in logic high state). when cs is in a logic high state, any signal at the sclk and mosi pin is ignored and miso is tristated (high impedance). mosi pin this pin is for the input of serial instruction data. mosi information is read in on the falling edge of sclk. to program the mc33389 by setting appropriate programming registers, an sixteen bit serial stream of data is required to be 40 100 60 120 80 140 typ sleep current (a) 16 v temperature (c) -50 0 50 100 150 -25 25 75 125 160 180 12 v 6.0v mosi cs sclk miso mosi miso mc68hcxx 33389
analog integrated circuit device data freescale semiconductor 31 33389 functional device operation logic commands and registers entered the mosi pin starting wit h bit15, followed by bit14, bit13, etc., to bit0. for each fall of the sclk signal, with cs held in a logic low state, a data bit is loaded into the shift register per the tidbit mosi stat e.the shift register is full after sixteen bits of information have been entered. miso pin the serial output (miso) pin is the tri-stateabl e output from the shift register. the miso pin remains in a high impedance state until the cs pin goes to a logic low state. the miso pin changes state on the rising edge of sclk and reads out on the falling edge of sclk. the mosi/miso shifting of data follows a first-in-first-out protoc ol with both input and output words transferring the msb first. module address map, the module address map is shown in table. control and status reporting of the 33389 the mcu is responsible for the control data transfer to the 33389, while the 33389 reports its status to the mcu. major data for control and status reporting are summarized here: ? spi initialization during start up ? 33389 control during operation ? watchdog triggering ? reading status registers of the 33389 control data the control data are transfe rred from the mcu to the 33389. a control word includes an address of a control register and the appropriate data (see figure 17 ). basically, the following data will be transferred. please see spi registers descriptions on page 34 . ? 33389 mode control ? supply control ? forced wake-up timing ? cyclic sense control ? watchdog control ? transceiver control status data the status data are transmitted from the 33389 to the mcu. after receiving a valid re gister address from the mcu, the 33389 returns the appropriate status. some of the major status data are listed below: ? current operation mode status ? wake-up sources ? reset status ? error status ? over temperature status ? transceiver status data transfer the data to and from the 33389 are transferred in form of two bytes.the structure of the transferred information is the same as for control and status reporting. the address field a5 to a0 (bit 15 to bit 10) contai ns the address of a control or status register in the 33389. rw (bit 9 and bit 8) contains the read/write flag for the data field. the parity field is located at p3 to p0 (bit 7 to bit 4). the dat a field d3 to d0 (bit 3 to bit 0) is part of the two-byte data word. please see figure 17 . table 16. module address map address register register name $000 mode control register mcr $003 mode control validation registermcvr mcvr $005 v3 control register v3r $006 cyclic timing control register cytcr $009 software watchdog control register swcr $00a ground shift level register gslr $00c wake-up input control register wuicr $00f wake-up input status register wuisr $011 wake up input real time information wuirti $012 overtemperature status regist otsr $014 transceiver error status register for canh tesrh $017 transceiver error status register for canl tesrl $018 reset source register rsr $01b voltage supply status regist vssr $01d interrupt mask control register 1 imr1 $01e interrupt mask control register 2 imr2 $021 interrupt source register 1 isr1 $022 interrupt source register 2 isr2 $024 transceiver control register tcr table 16. module address map address register register name
analog integrated circuit device data 32 freescale semiconductor 33389 functional device operation logic commands and registers figure 17. spi communication format the sbc is accessible via the spi interface in the normal request mode, normal mode, and stand-by mode. in all other modes (sleep mode, emergency mode), the voltage supply for the microcontroller in permanently switched off and the sbc input logic for miso, mosi, cs and sclk isn?t working (except spi wake-up function in the sleep mode). writing data to write data in a spi register there are two, one-byte transmissions to be performed. the first byte contains the address of the register (msb first) and the read/write bits must be set to one. the second byte contains the new data addressed by the previous byte (msb first) and the parity information. the calculation of the parity field p3-p0 has to follow the equations: note: during the transmissi on of the two bytes the cs pin remains 0. please see figure 18 figure 18. microcontroller spi writing data the sbc sends back the old address, r/w, parity, and data information from a previous transmission. this data contains no useful information (e.g. status). it shouldn?t be used. in case of a wrong address field or parity mismatch, an interrupt will be issued and the sbc retains the old state. reading data to read data from a dedicated register two, one-byte transmissions have to be performed. the first byte contains the address of the register (msb first) and the read/write flags setting to zero. the second byte needn?t contain valid data, nevertheless, the parity calculat ion has to performed to avoid an interrupt caused by a parity mismatch. during a read operation the sbc sends back the old address and r/w bits and the new data addressed by the first transmitted byte starting with p3 after the last valid read/write bit has been received. note: during the transmissi on of the two bytes the cs pin remains zero. a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 p3 p2 p1 p0 rw rw bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 address + r/w data parity mosi miso p3 = d3 d0 (ex - or) p2 = d3 d2 p1 = d2 d1 p0 = d1 d0 a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 p3 p2 p1 p0 rw rw a3 a2 a1 a0 1 1 a5 a4 sbc spi data register bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hc08/12 spi data register old address + r/w old data old parity new address + r/w (1st byte) new data + parity (2nd byte) d3 d2 d1 d0 p3 p2 p1 p0
analog integrated circuit device data freescale semiconductor 33 33389 functional device operation logic commands and registers figure 19 illustrates content of the hc08/12 spi data register and the sbc spi data register before the transmission. the new address and r/w bits are already in the spi data register while the new data and parity bits are still in an appropriate microcontr oller register or memory. this second byte has to be loaded into the hc08/12 spi data register after the first byte was transmitted to the sbc. figure 19. microcontroller spi reading data - sequence a after transmission of the first byte, the hc08/12 spi read buffer contains the old address and r/w bits received from the sbc. an appropriate operation in the microcontro ller loads the new data and parity into the hc08/12 spi data r egister (second byte). in the sbc the internal logic loads p3-p0 and d3-d0 to the location of bit 15 to bit 8 in the sbc spi data register, shifting t his data within the rema ining eight clock cycles. please see figure 20 . figure 20. microcontroller spi reading data - sequence b after sixteen clock cycles, the microcontrollers read buffer cont ains the new parity, and data and is now ready for the next transmission. please see figure 21 . a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 p3 p2 p1 p0 rw rw a3 a2 a1 a0 0 0 a5 a4 000000 00 sbc spi data register bit14 bit13 bit12 bit11 bit10 bit9 bit8 b it7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hc08/12 spi data register old address + r/w old data old parity new address + r/w (1st byte) new data + parity (2nd byte) a5 a4 a3 a2 a1 a0 d3 d2 d1 d0 p3 p2 p1 p0 0 0 000000 00 sbc spi data register bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 hc08/12 spi data register new address + r/w new data new parity addressed by the new address bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 a3 a2 a1 a0 rw rw a5 a4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 old address + r/w in hc08/12 spi read buffer
analog integrated circuit device data 34 freescale semiconductor 33389 functional device operation logic commands and registers figure 21. microcontroller spi reading data - sequence c safety concept because the spi interface is an on-board interface without any data fault detection capabilitie s, the spi interface of the 33389 provides built-in fail save functions. address coding is based on increasing the hamming distance, parity check, a nd parity generation for data. for the address and the read/w rite bits, only codes with a hamming distance < 2 will be used. so, any single bit failure caused by disturbances will be recognized and handled. when one bit toggles in the address field during the transmission, no misbehavior occurs. additionally, validation registers are implemented to confirm safety critical settings in the 33389, e.g. the mode control register mcr has its validation register, mcvr. to change the appropriate settings, both registers must have the same content to switch to another mode. to increase data integrity, a parity check is used. a parity module in the 33389 ascertains the parity of the data field and compares the result with the re ceived parity. when the parity check is successfully passed, data will be written into the addressed registers. the parity bits p3 to p0 results from the logic following equations: in case of error detection, the incoming data is not taken in the sbc and an error flag is set in an spi register. spi registers descriptions registers mcr and mcvr control the sbc mode. to change the operating mode of the sbc, both registers must have the same content. the order of writing the registers has to be taken into account. to properly set the sbc mode, mcr must be written first follow ed by the mcvr write. a write operation sets the mcr and mcvr registers. the emergency mode is a regular mode. a reset of both mcr and mcvr registers occurs when rst = low and the sbc is set to normal request mode. p1 p0 d3 d2 d1 d0 p3 p2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 new parity + new data in hc08/12 spi read buffer a5 a4 a3 a2 a1 a0 0 0 0 0 0 0 0 0 rw rw a3 a2 a1 a0 0 0 a5 a4 sbc spi data register bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 hc08/12 spi data register old address + r/w old data old parity p3 = d3 d0 (ex - or) p2 = d3 d2 p1 = d2 d1 p0 = d1 d0 table 17. mode control register (mcr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcr $000 r msr2 msr1 msr0 w mcr2 mcr1 mcr0 reset ? ? ? ? ? 0 0 0
analog integrated circuit device data freescale semiconductor 35 33389 functional device operation logic commands and registers this register configures the state of v3 high-side switch in normal and stand-by mo des, and the v3 operation and the forced wake-up or the cyclic sense option for the sleep mode operation. in low power modes, cyclic sense has priority. a reset of the register occurs when rst = low. this register is used to select t he cyclic sense or force wake-up timing. table 18. mode control validating register (mcvr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mcvr $003 r msvr2 msvr1 msvr0 w mcr2 mcr1 mcr0 reset ? ? ? ? ? 0 0 0 table 19. mcr and mcvr bit definition mc(v)r2 mc(v)r1 mc(v)r0 ? msr2 msr1 msr0 automatically entered after reset normal request 0 0 0 0 0 1 normal 0 0 1 0 1 0 stand-by 0 1 0 1 0 0 sleep 1 0 0 1 1 1 emergency 1 1 1 table 20. v3 control register (v3r) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 v3r $005 r wi2v3 fwu cys v3r0 w reset ? ? ? ? 1 0 0 0 table 21. v3r bit definition wi2v3 fwu cys v3r0 ? comments x 0 0 0 v3 off only in normal and stand-by mode available x 0 0 1 v3 on x x 1 x cyclic sense on ? x 1 0 x forced wake-up on only in sleep mode available 1 x x x wake-up inputs linked to v3 table 22. cyclic timing control register (cytcr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 cytcr $006 r cytcr2 cytcr1 cytcr0 w reset ? ? ? ? ? 0 0 0
analog integrated circuit device data 36 freescale semiconductor 33389 functional device operation logic commands and registers this register is used to select the window watchdog time period. open window of the selected pe riod is only the second half of the selected period. this register is used to monitor the ground shift of the vehicle network. table 23. cytcr bi t definition cytcr2 cytcr1 cytcr0 comments t(ms) typical 0 0 0 timer on, t1 (default) 32 0 0 1 timer on, t2 64 0 1 0 timer on, t3 128 0 1 1 timer on, t4 256 1 0 0 timer on, t5 512 1 0 1 timer on, t6 1024 1 1 0 timer on, t7 2048 1 1 1 timer on, t8 8192 note: a reset of the register occurs when rst = low. table 24. software watchdog control register (swcr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 swcr $009 r swcr2 swcr1 swcr0 w reset ? ? ? ? ? 0 0 0 table 25. swcr bit definition swcr2 swcr1 swcr0 comments t(ms) typical 0 0 0 timer on, t1 (default) 5 0 0 1 timer on, t2 10 0 1 0 timer on, t3 20 0 1 1 timer on, t4 33 1 0 0 timer on, t5 50 1 0 1 timer on, t6 75 1 1 0 timer on, t7 100 1 1 1 timer on, t8 200 note: the software watchdog is only running in normal and stand-by modes. a reset of this register occurs when rst = low. table 26. ground shift level register (gslr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 gslr $00a r txdom shift gslr1 gslr0 w reset ? ? ? ? ? 0 0 0
analog integrated circuit device data freescale semiconductor 37 33389 functional device operation logic commands and registers this register configures the wake-u p level for the l0, l1, and l2 inputs. it reports the can wake-up and spi ( cs ) wake-up events during the read operation. this register reads back the wake input (l0, l1, l2) causing the sbc to wake-up. table 27. gslr bit definition gslr1 gslr0 typical ground shift level 0 0 0.7 v 0 1 -1.2 v 1 0 -1.7 v 1 1 -2.2 v shift 1 = ground shift above the threshold selected by gslr1 and gslr2 0 = no ground shift the shift information is latched until a read operation of the gslr register occurs. the gslr register is set to 0 after power- on reset. a reset of gslr1 and gslr0 occurs when rst = low. txdom 0 = no failure on tx 1 = tx permanent dominant table 28. wake-up input control register (wuicr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wuicr $00c r spiwu buswu wucr1 wuicr0 w reset ? ? ? ? 0 0 0 0 table 29. wuicr bit definition wuicr1 wuicr0 description 0 0 wake-up inputs disabled 0 1 positive edge sensitive 1 0 negative edge sensitive 1 1 positive and negative sensitive table 30. wuicr bit definition spiwu buswu description 0 0 no wake-up events 0 1 wake-up event on can bus 1 0 wake-up event on spi bus the information is spiwu and buswu is latched. bits spiwu and buswu will be reset by a read operation of the wuicr register and are set to 0 after a power-on reset. a reset of wuicr1 and wuicr0 occurs when rst = low. table 31. wake-up input status register (wuisr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wuisr $00f r wuisr2 wuisr1 wuisr0 w reset ? ? ? ? ? 0 0 0
analog integrated circuit device data 38 freescale semiconductor 33389 functional device operation logic commands and registers this register reports the real time inform ation on the state; (high or low) of the l0, l1, and l2 inputs. the bits wuirt1 2:0 contain the real time logic value coming from the wake-up inputs (0 means input below threshold, 1 means input above threshold. typical threshold is 3.5 v). this register reports the canh failure status. table 32. wuisr bit definition wuisr2 wuisr1 wuisr0 description 0 0 0 no event on wake-up inputs x x 1 event on l0 x 1 x event on l1 1 x x event on l2 in case of a wake-up event, the appropriate bit is set to 1. the bits will be reset by a read operation of the register. after power-on reset, all bits are set to 0. table 33. wake-up input real time information (wuirti) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 wuirti $011 r wuirti2 wuirti1 wuirti0 w reset ? ? ? ? ? 0 0 0 table 34. over temperature status register (otsr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 otsr $012 r opwv2 opwv1 optv2 otv1 w otv2c reset ? ? ? ? 0 0 0 0 this register reads back the over temperatur e status for the v1 and v2 regulators. it is used to turn v2 on after a v2 over tem - perature shutdown occurred in the write mode. otv1: 1 = v1 over temperature shutdown, 0 = v1 no over temperature otv2: 1 = v2 over temperature shutdown, 0 = v2 no over temperature opwm1: 1 = v2 over temperature pre-warning, 0 = v2 normal temperature opwv2: 1 = v2 over temperature pre-warning, 0 = v2 normal temperature in case of v1 or v2 over temperature, the appropriate volt age regulators are switched off autom atically, and the over temperatu re flags are set (latched). the flags can be reset by a read operation of the register otsr. once v2 is switched off because of ov er temperature (otv2 = 1 ) it can only be switched on again by fo rcing otv2c = 0 by a write operation. the v1 and v2 pre-warning flags are set as long as the first over temperature exists. the flags disappear, when the temperature is below the threshold. an over temperature of the v2 power supply will also switch off v3. after a power-on reset, all bits of th e reg - ister are set to 0. table 35. transceiver error stat us register for canh (tesrh) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tesrh $014 r tesrh3 tesrh2 tesrh1 tesrh0 w reset ? ? ? ? 0 0 0 0
analog integrated circuit device data freescale semiconductor 39 33389 functional device operation logic commands and registers . this register reports the canl and tx permanent failure status this register monitors the status of the v2, v3, and v bat voltage level. table 36. tesrh bit definition tesrh3 tesrh2 tesrh1 tesrh0 description 0 0 0 0 no failure on canh 0 x 0 1 canh wire interruption x x 1 x canh short circuit to v bat 0 1 0 x canh short circuit to ground 1 x 0 x canh short circuit to v cc in case of canh line failures, the appropriate bit(s) are set according to table 36 . this information is latched. the register can be reset by a read operation. after power-on is reset, all bits are set to 0. table 37. transceiver error status register for canl and tx (tesrl) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tesrl $017 r tesrl3 tesrl2 tesrl1 tesrl0 w reset ? ? ? ? 0 0 0 0 table 38. tesrl bit definition tesrl3 tesrl2 tesrl1 tesrl0 description 0 0 0 0 no failure 0 x 0 1 canl wire interruption 0 1 0 x canl short circuit to ground/ca nh mutually shorted to canl x x 1 x canl short circuit to v bat 1 x 0 x canl short circuit to v dd in case of canl line failures, the appropriate bit(s) are set according to table 38 . this information is latched. t he register can be reset by a read operation. after power-on is reset, all bits are set to 0. table 39. reset source register (rsr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 rsr $018 r rsr2 rsr1 rsr0 w reset ? ? ? ? ? 1 0 1 this register reports the sour ce of a reset already occurred. rsr0: 1 = > v dd1 under voltage occurred (rsr2 = 1 in this case), 0 = > no over voltage on v occurred rsr1: 1 = > software watchdog reset occurred (rsr 2 = 1 in this case), 0 = > no sw watchdog reset occurred rsr2: 1 = > external reset occurred (rsr0 = rsr1= 0 in this case), 0 = > no external reset occurred events related to the bits in register rsr are latched. all bits can be reset by a read operation of the register. after a powe r-on reset, rsr2 and rsr0 are set to 1. therefore, the first read out of the register after power-on delivers rsr[2:0] = [101]. table 40. voltage supply st atus register (vssr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 vssr $01b r v3sr v2sr vbsr1 vbsr0 w reset ? ? ? ? 0 0 ? ? por ? ? ? ? 0 0 0 1
analog integrated circuit device data 40 freescale semiconductor 33389 functional device operation logic commands and registers the next two registers (imr1 and imr2) mask the interrupt function. the next two registers (isr1 and isr2) read the interrupt source. all bits in registers isr1 and isr2 are copies of the appropriate bits in different spi registers. for a faster read -out, these bits are merged in isr1 and isr2. a reset cannot be completed for registers isr1 and isr2. table 41. vbsr1 vbsr0 vbsr1 vbsr0 description 0 0 no failure on vbat x 1 under voltage (batfail) 1 x over voltage (bathigh) v2sr: 1 = v2 on, 0 = v2 off v3sr: 1 = v3 over temperature, 0 = v3 no over temperature vbsr1 is real time information. it cannot be reset. bits v3sr , v2sr, and vbsr0 are latched and can be reset by a read operation of the register. table 42. interrupt mask control register 1 (imr1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 imr1 $01d r hv htpw mtpw batu w reset ? ? ? ? 0 0 0 0 table 43. interrupt mask control register 2 (imr2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 imr2 $01e r busf spie wu w reset ? ? ? ? ? 0 0 0 to enable the appropriate interrupt, the mask bit has to be set to 1. to disable the interrupt the bit, it must be cleared to 0 . after a power-on reset or rst = low, the bits are cleared to 0. all interrupt s are disabled. explanatio n for the abbreviations: hv = v bat high voltage ht = high temperature on v1 or v2 mtpw = medium temperature pre-warning on v1 or v2 batu = battery under voltage (batfail) busf = can bus failure spie = spi error wu = wake-up table 44. interrupt source register 1 (isr1) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 isr $021 r hv htpw mtpw batu w reset ? ? ? ? 0 0 0 0 table 45. interrupt source register 2 (isr2) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 isr $022 r busf spie wu w reset ? ? ? ? ? 0 0 0
analog integrated circuit device data freescale semiconductor 41 33389 functional device operation logic commands and registers this register controls the st ate of the can transceiver (can transceiver is also dependent upon the sbc mode). when it is read, this register reports the can transceiver state and a can over temperature condition. table 46. transceiver control/status register (tcr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 tcr $024 r tot tsr2 tsr1 tsr0 w tcr2 tcr1 tcr0 reset ? ? ? ? 0 0 0 0 table 47. tcr / tsr data tcr2 tcr1 tcr0 description tsr2 tsr1 tsr0 0 0 0 standard/term v bat 0 0 0 0 1 0 standard/rx only 0 1 0 0 1 1 standard/rxtx 0 1 1 tot 1 = > transceiver over temperature 0 = > normal temperature the mode bit selects between the standard and extended physical laye r mode. any conditions forcing the transceiver to term vbat lead to reset of tcr0 and tcro1 bits. after power-on reset all bits of th e register are set to 0. the information tot is latched. reset tot by read - ing the tcr. in case of rst = low, the register content remains unchanged.
analog integrated circuit device data 42 freescale semiconductor 33389 typical applications typical applications figure 22. typical application schematic 1 figure 23. typical application: v3 used as auxiliary ecu supply figure 24. reset duration extension v1 vbat v2 r st int cs miso mosi sck tx rx canh canl rtl rth v3 l0 l1 l2 c3 c4 c5 c6 c1 c2 rp0 rl rh gnd gnd can spi vdd int reset auxiliary 5v auxiliary 12v s0 rs0 cl0 rp1 s1 rs1 cl1 rp2 s2 rs2 cl2 ignition can bus 33389 vbat v3 l0 l1 l2 c1 c2 rp0 gnd auxiliary s0 rs0 cl0 rp1 s1 rs1 cl1 rp2 s2 rs2 cl2 ignition switch local 12v 33389 v1 r st c3 c4 vdd reset 33389 cr micro
analog integrated circuit device data freescale semiconductor 43 33389 typical applications figure 25. typical application schematic 2 the sbc offers several capabilities to help users debug their application. ? external bias of v1 and reset pin ? turn off software watchdog in the stand-by mode ? special debug samples with software watchdog disable at power-up (contact local motorola representative) debug and program download into flash memory while the sbc is powered, it enters normal request mode and expects during the 75 ms ti me period in the nr mode, an spi trigger word (to enter normal mode and select the watchdog time period). if this does not occur, the sbc enters the sleep mode and turns off v1. when the software is debugged, and when using development tools, it is not always easy to make sure these events happen properly. it is thus possible to externally power the v1 line with an external 5.0 v supply, and to force the reset pin to v1 or to and external 5.0 v. these can be done at nominal voltage and tem perature. by doing this, 5.0 v is provided to the mcu v dd and reset lines. under this condition the sbc is not operational. however, the reset pin is pulled low and is sinking 5 ma to ground. this means, the external circuitry driving reset must have a current capability higher than 5 ma in order to drive the reset in the high-state. disable of software watchdog in stand- by mode the software watchdog can be disable in stand-by mode only. in order to disable it the following operation must be done: ? write to mcr register?data 011 (bit 2, bit 1, bit 0) ? write to mcvr register?data 011 (bit 2, bit 1, bit 0) then the sbc enters the stan d-by mode without software watchdog. however the v2 can not be turn on, and the can cell can not be used. (wake-up input linked to peripheral circuits: (ex: low speed can or lin transceivers). v1 vbat v2 r st int cs miso mosi sck tx rx canh canl rtl rth v3 l0 l1 l2 c5 c6 c1 c2 rp0 rl rh gnd gnd can 1 spi vdd int reset auxiliary 5v auxiliary 12v s0 rs0 cl0 ignition can bus # 1 canh canl rtl rth rl rh can bus # 2 gnd inh mc33388 lin 1k lin bus gnd inh mc33399 +12v vbat vdd vsup can 2 sci spi bus tx/rx tx/rx 33389
analog integrated circuit device data 44 freescale semiconductor 33389 packaging package dimensions packaging package dimensions for the most current package revision, visit www.freescale.com and perform a keyword search using the 98ash70273a listed below. dh suffix vw suffix (pb-free) 20 pin plastic package 98ash70273a issue e
analog integrated circuit device data freescale semiconductor 45 33389 packaging package dimensions dh suffix vw suffix (pb-free) 20 pin plastic package 98ash70273a issue e
analog integrated circuit device data 46 freescale semiconductor 33389 packaging package dimensions dw suffix eg suffix (pb-free) 28 pin plastic package 98asb42345b issue g
analog integrated circuit device data freescale semiconductor 47 33389 packaging package dimensions dw suffix eg suffix (pb-free) 28 pin plastic package 98asb42345b issue g
analog integrated circuit device data 48 freescale semiconductor 33389 revision history revision history date description of changes 5.0 3/2007 ? added revision history ? converted to the prevailing freescale form and style ? entire document was edited for wording, labels, and technical accuracy. ? added the pb-free package types vw and eg to the ordering information ? updated the package drawings ? added peak package reflow temperature during reflow (4) , (5) on page 7 ? added notes (4) and (5) ? removed all references to mc33389adw/r2, mc33389adh/r2, mc33389ceg/r2, and mc33389deg/r2 from the data sheet. ? restated mc33389ddw in the device variations on page 2
mc33389 rev. 5.0 3/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

▲Up To Search▲

Price & Availability of 33389

	To Download 33389 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .